Phase-change memory arrays are based upon memory elements that switch among two material phases, or gradations thereof, to exhibit corresponding distinct electrical characteristics. Alloys of elements of group VI of the periodic table, such as Te or Se, referred to as chalcogenides or chalcogenic materials, can be used advantageously in phase change memory cells. In the chalcogenides, the resistivity varies by two or more orders of magnitude when the material passes from the amorphous (more resistive) phase to the crystalline (more conductive) phase, and vice versa. In the amorphous state, moreover, the resistivity depends to a marked extent upon the temperature, with variations of approximately one order of magnitude every 100° C.
A chalcogenide memory device may utilize the wide range of resistance values available for the material as the basis of memory operation. Each resistance value corresponds to a distinct structural state of the chalcogenide material and one or more of the states can be selected and used to define operational memory states. Chalcogenide materials exhibit a crystalline state, or phase, as well as an amorphous state, or phase. Different structural states of a chalcogenide material differ with respect to the relative proportions of crystalline and amorphous phase in a given volume or region of chalcogenide material. The range of resistance values is generally bounded by a set state and a reset state of the chalcogenide material. By convention, the set state is a low resistance structural state whose electrical properties are primarily controlled by the crystalline portion of the chalcogenide material and the reset state is a high resistance structural state whose electrical properties are primarily controlled by the amorphous portion of the chalcogenide material.
Phase change may be induced by increasing the temperature locally. Below 150° C., both of the phases are relatively stable. Above 200° C. and at temperatures less than those necessary for reset, there is an increase in nucleation of the crystallites and, if the material is kept at the crystallization temperature for a sufficiently long time, it undergoes a phase change and becomes crystalline. This crystalline state is then retained whether the material is cooled rapidly or slowly. To bring the chalcogenide back to the amorphous state it is necessary to raise the temperature above the melting temperature (approximately 600° C.) and then cool it off rapidly. If instead, the material is cooled slowly, increased degrees of crystallization result after cooling. From the electrical standpoint, it is possible to reach the crystallization and melting temperatures by causing a current to flow through a crystalline resistive element that heats the calcogenic material by the Joule effect.
Each memory state of a chalcogenide memory material corresponds to a distinct resistance value and each memory resistance value signifies unique informational content. Operationally, the chalcogenide material can be programmed into a particular memory state by providing an electric current pulse of an appropriate amplitude and duration to transform the chalcogenide material into the structural state having the desired resistance. By controlling the amount of energy provided to the chalcogenide material and rate of cooling after heating, it is possible to control the relative proportions of crystalline and amorphous phase regions within a volume of the material and to thereby control the structural (and corresponding memory) state of the chalcogenide material to store information.
Each memory state can be programmed by providing the current pulse characteristics of the state and each state can be identified, or “read”, in a non-destructive fashion by measuring the resistance at currents significantly less than those necessary for programming; e.g. less than half the current necessary to crystallize the material. Programming among the different states is reversible and the memory devices can be written and read over a large number of cycles with robust and reliable operation until one of the states deteriorates, signaling the endurance limit has been reached for that bit. The variable resistance memory functionality of chalcogenide materials is currently being exploited in the OUM (Ovonic Universal (or Unified) Memory) devices that are beginning to appear on the market. Basic principles and operation of OUM type devices are presented, for example, in U.S. Pat. Nos. 6,859,390; 6,774,387; 6,687,153; and 6,314,014; the disclosures of which are incorporated by reference herein, as well as in several journal articles including, “Low Field Amorphous State Resistance and Threshold Voltage Drift in Chalcogenide Materials,” published in EE transactions on Electron Devices, vol. 51, p. 714-719 (2004) by Pirovana et al.; and “Morphing Memory,” published in Science News, vol. 167, p. 363-364 (2005) by Weiss.
The behavior (including switching, memory, and accumulation) and chemical compositions of chalcogenide materials have been described, for example, in the following U.S. Pat. Nos. 6,671,710; 6,714,954; 6,087,674; 5,166,758; 5,296,716; 5,536,947; 5,596,522; 5,825,046; 5,687,112; 5,912,839; and 3,530,441, the disclosures of which are hereby incorporated by reference. These references present proposed mechanisms that govern the behavior of chalcogenide materials. The references also describe the structural transformations from the crystalline state to the amorphous state (and vice versa) via a series of partially crystalline states in which the relative proportions of crystalline and amorphous regions vary during the operation of electrical and optical chalcogenide materials.
A wide range of chalcogenide compositions has been investigated in an effort to optimize the performance characteristics of chalcogenic devices. Chalcogenide materials generally include a chalcogen element and one or more chemical or structural modifying elements. The chalcogen element (e.g. Te, Se, S) is selected from column VI of the periodic table and the modifying elements may be selected, for example, from column III (e.g. Ga, Al, In), column IV (e.g. Si, Ge, Sn), or column V (e.g. P, As, Sb) of the periodic table. The role of modifying elements includes providing points of branching or cross-linking between chains comprising the chalcogen element. Column IV modifiers can function as tetracoordinate modifiers that include two coordinate positions within a chalcogenide chain and two coordinate positions that permit branching or crosslinking away from the chalcogenide chain. Column III and V modifiers can function as tricoordinate modifiers that include two coordinate positions within a chalcogenide chain and one coordinate position that permits branching or crosslinking away from the chalcogenide chain. Embodiments in accordance with the principles of the present invention may include binary, ternary, quaternary, and higher order chalcogenide alloys. Examples of chalcogenide materials are described in U.S. Pat. Nos. 5,166,758, 5,296,716, 5,414,271, 5,359,205, 5,341,328, 5,536,947, 5,534,712, 5,687,112, and 5,825,046 the disclosures of which are all incorporated by reference herein. Chalcogenide materials may also be the resultant of a reactive sputtering process: a chalcogenide nitride, or oxide, for example and chalcogenide may be modified by an ion implantation or other process.
Early work in chalcogenide devices demonstrated electrical switching behavior in which switching from a resistive state to a conductive state was induced upon application of a voltage at or above the threshold voltage of the active chalcogenide material. This effect is the basis of the Ovonic Threshold Switch (OTS) and remains an important practical feature of chalcogenide materials. The OTS provides highly reproducible switching for over 10 cycles. Basic principles and operational features of the OTS are presented, for example, in U.S. Pat. Nos. 3,271,591; 5,543,737; 5,694,146; and 5,757,446; the disclosures of which are hereby incorporated by reference, as well as in several journal articles including “Reversible Electrical Switching Phenomena in Disordered Structures,” Physical Review Letters, vol. 21, p. 1450-1453 (1969) by S. R. Ovshinsky; “Amorphous Semiconductors for Switching, Memory, and Imaging Applications,” IEEE Transactions on Electron Devices, vol. ED-20, p. 91-105 (1973) by S. R. Ovshinsky and H. Fritzsche; the disclosures of which are hereby incorporated by reference. Three-terminal OTS devices are disclosed, for example, in U.S. Pat. Nos. 6,969,867 and 6,967,344; the disclosures of which are hereby incorporated by reference.
In order to limit the power consumption of phase change memories and, in part, to thereby ensure that phase change memories are fully compatible with existing technologies, such as CMOS technologies, a great deal of effort has been expended towards reducing the energy required to program a phase change memory. Nevertheless, significant currents are required to program the devices. As a result, the current sources that supply programming current to the devices are typically quite robust. In order to supply the relatively large currents required to program the devices, the current sources typically employ large, high current-capacity, active devices that occupy a significant amount of chip area—“real estate.” A method and apparatus to reduce the size of active devices employed within a phase change memory programming current source would therefore be highly desirable to reduce cost by reducing related chip area. For clarity and brevity of description, the following discussion will be limited to binary phase change memories, but multi-level phase change memories are contemplated within the scope of the invention. The distinct electrical characteristics are associated with two different crystallographic structures of the material forming the memory element. An amorphous, disorderly, phase is associated with a relatively high resistivity and a crystalline or polycrystalline phase is associated with a relatively low resistance. The techniques described herein may be extended to any variable resistance technology by those reasonably skilled in the art.